1. Field of the Invention
The present invention relates to a synchronous signal transfer and processing device for transferring a signal/data in accordance with a clock signal. More specifically, the present invention relates to a configuration for avoiding racing on the signal transfer path of the synchronous type signal transfer and processing device.
2. Description of the Background Art
A clock synchronous processing scheme of transferring and processing a signal synchronously with a clock signal is normally employed for high speed signal/data processing. According to this synchronous processing scheme, data/signal is transferred and processed by controlling the operation state of a latch circuit or a flip-flop circuit for holding the data/signal in synchronization with a clock signal.
The synchronous processing scheme for transferring and processing a signal synchronously with a clock signal allows a signal/data to be processed in a pipeline fashion, achieving high-speed processing. In addition, since signal/data (to be simply referred to as “data” hereinafter) processing timing and data transfer timing are determined by a clock signal, a margin for processing start timing can be decreased and high-speed data processing can be implemented. Further, since a data processing cycle is determined by a clock signal cycle, high-speed processing is achieved.
According to the above-stated clock synchronous processing scheme, clock signals as same in timing and less different in phase as possible should be transferred to many latch circuits or flip-flop circuits, in order to allow these latch/flip-flop circuits to operate at the same timing. For that reason, various clock distribution schemes are employed to transmit a main clock signal from a clock input buffer or the like with a clock skew as small as possible. These clock distribution schemes include a clock tree scheme for transmitting clock signals to the respective latch or flip-flop circuits through clock branch paths arranged in a tree-like form, a clock mesh scheme for transmitting a main clock signal through clock distribution paths arranged in a meshed form, a fishbone scheme for providing a branch path on a main clock transmit line extending almost linearly, driving this branch path by a clock driver and transferring clock signals to the respective latch or flip-flop circuits and the like.
FIG. 28 shows an example of the configuration of a conventional synchronous data processing and transfer device. In FIG. 28, the clock tree scheme is employed as the clock distribution scheme by way of example.
In FIG. 28, a clock distribution system includes a clock driver DR0 for buffering a main clock signal MCLK, and clock drivers (repeaters) DR1a to DR1c, arranged at predetermined intervals on a clock distribution path LP0 coupled to a clock distribution node ND0, for buffering clock signals on clock distribution path LP0, respectively. Clock drivers DR1a to DR1c transmit the clock signals to clock branch paths LP1a to LP1c coupled to clock distribution nodes ND1a to ND1c, respectively.
Parasitic capacitance Ca and parasitic resistance Ra exist on clock distribution path LP0. In addition, parasitic resistance Rb and parasitic capacitance Cb due to interconnection line capacitance and resistance also exist on clock transmission lines driven by clock drivers DR1a to DR1c, respectively.
In these clock distribution routes, main clock signal MCLK from clock driver DR0 is transmitted through clock distribution paths arranged in a tree-like form. The distribution paths arranged in a tree-like form are arranged symmetrically with respect to clock driver DR0 transmitting main clock signal MCLK so that the paths transmitting the clock signals are made equal in delay time. On each respective branch path of this clock tree, a signal propagation path between a clock terminating node of the final stage and a main cock signal input node is set to have as equal interconnection line delay as possible to make clock skews on respective clock terminating nodes as small as possible.
Signal processing related circuitry includes latch circuits LTa to LTc arranged corresponding to clock drivers DR1a to DR1c, respectively. Latch circuits LTa and LTc have the same configuration and operate in a common phase. Latch circuit LTb operates in a reversed phase to latch circuits LTa and LTc. Specifically, each of latch circuits LTa and LTc includes an inverter IVa that receives clock signal CLK from the corresponding clock driver, a transfer gate TXa that is rendered conductive, when clock signal CLK from the corresponding clock driver is at H level, to pass a signal received from the circuit in a preceding stage, an inverter IVb that receives the signal transmitted through transfer gate TXa, an inverter IVc that inverts the output signal of inverter IVb and transmits the inverted output signal to the circuit at the next stage, and a tri-state inverter TVa that is made active, when the output signal of inverter IVa is at H level, to invert the output signal of inverter IVb for transmission to the input node of inverter IVb.
Latch circuit LTb includes an inverter IV1 which receives clock signal CLK from corresponding clock driver DR1b, a transfer gate TXb which is made conductive, when the output signal of inverter IV1 is at H level, to pass a signal transmitted from the circuit in a preceding stage, an inverter IV2 which receives the signal transmitted through transfer gate TXb, an inverter IV3 which inverts the output signal of inverter IV2 and transmits the inverted output signal to the circuit at the next stage, and a tri-state inverter TV1 which is made active, when clock signal CLK from corresponding clock driver DR1b is at H level, to invert the output signal of inverter IV2 for transmission to the input node of inverter IV2.
A delay circuit DLa is interposed between latch circuits LTa and LTb. A delay circuit DLb is interposed between latch circuits LTb and LTc. These delay circuits DLa and DLb are provided for preventing data to be latched from being rewritten by an applied signal if latch circuits LTa to LTc simultaneously turn into a transparent state due to a clock skew.
As shown in FIG. 28, on the clock distribution path, clock drivers DR1a to DR1c are arranged corresponding to latch circuits LTa to LTc, respectively so that clock transmission paths from main clock signal MCLK to respective latch circuits LTa to LTc have same a signal transmission delay as possible. It is intended to make the operation timing of each of latch circuits LTa to LTc as same as possible to achieve synchronous data transfer.
In this arrangement, when transfer gates TXa turn conductive in respective latch circuits LTa and LTc and latch circuits LTa and LTc turn into a transparent state of passing an applied signal, transfer gate TXb of latch circuit LTb is in a nonconductive state, and latch circuit LTb is in a latching state. Therefore, the output data of latch circuit LTa is not captured by latch circuit LTb and latch circuit LTc transmits latch data of latch circuit LTb to the circuit at the next stage. On the other hand, when transfer gates TXa of respective latch circuits LTa and LTc are nonconductive and latch circuits LTa and LTc are in a latching state, transfer gate TXb of latch circuit LTb is in a conductive state and latch circuit LTb is in a transparent state. Therefore, latch circuit LTb transmits the latched data of latch circuit LTa to latch circuit LTc at the next stage.
As shown in FIG. 28, by alternately setting latch circuits LTa to LTc in the transparent state and latching state, it is possible to sequentially transfer data from latch circuits LTa to LTc synchronously with clock signal CLK.
However, line parasitic resistance and line parasitic capacitance exist on each of clock distribution paths LP0 to LP1c shown in FIG. 28. If the lengths of the clock transmission paths are equal for all latch circuits LTa to LTc, the clock transmission paths for latch circuits LTa to LTc have the same clock propagation delay and a clock skew is hardly caused. However, the clock distribution paths differ in interconnection length, and therefore in parasitic resistance and parasitic capacitance, according to the arranged positions of latch circuits LTa to LTc. Thus, a clock skew occurs in clock signals CLK transmitted from clock drivers DR1a to DR1c to respective latch circuits LTa to LTc.
FIG. 29 is a timing chart representing the operations of the circuit device shown in FIG. 28 when a clock skew occurs. In FIG. 29, a clock skew occurs in clock signal CLK arriving at latch circuits LTa to LTc due to the difference in interconnection line delay. FIG. 29 shows an example of a state in which clock signal CLK arrives at the node (clock input node) NA of transfer gate TXa of latch circuit LTa earliest and arrives at the control node NB of transfer gate TXb of latch circuit LTc latest.
If a clock skew occurs as shown in FIG. 29, a period, in which both the control signals at control nodes (clock input nodes) NA and NB of latch circuits LTa and LTb become H level, is caused. If latch circuit LTa takes in an applied signal synchronously with the rise of clock signal CLK for transference to the circuit at the next stage, when transfer time for transferring data from latch circuit LTa to latch circuit LTb is shorter than an overlap period in which both the control signals at clock input nodes NA and NB are at H level, data to be latched by latch circuit LTb is rewritten by the data taken in by latch circuit LTa, and an erroneous rewriting occurs. This malfunction is generated due to the competition between the clock signal and the data, and therefore, it is referred to as “racing”.
To prevent such racing, delay circuits DLa and DLb are arranged as shown in FIG. 28. By arranging delay circuit DLa, time required for transmitting data DA captured by latch circuit LTa to the input of latch circuit LTb is made longer than an overlap period TS as shown in FIG. 30. In this arrangement, even if latch circuits LTa and LTb both turn into a transparent state, the latched data of latch circuit LTb is not rewritten by new data DA, making it possible to avoid racing.
However, if delay circuits DLa and DLb are arranged on the data transmission path, the number of components of logical gates disadvantageously increases and a layout area and power dissipation disadvantageously increases.
Further, the following procedure is required in an actual analysis of a circuit operation. Timing verification is performed for each signal transmission path. The clock timing of each latch circuit is adjusted based on the result of the timing verification. Therefore, it is necessary to interpose delay circuits, taking into account an optimum delay amount which do not influence the setup times of the latch circuits.
Specifically, as shown in FIG. 31, if data DA is transferred, valid data is transferred and latched by, for example, latch circuit LTa after clock signal CLK rises and then delay time TD of the delay circuit in the preceding stage passes. It is necessary to turn the latched data of latch circuit LTa into a definite state before clock signal CLK rises and latch circuit LTa enters a latching state. Time period in which this latched data is held in a definite state before the latch circuit enters a latching state is referred to as “setup time Tsu”.
Accordingly, if the cycle time of clock signal CLK is determined, when delay time TD becomes longer, setup time Tsu becomes shorter. In this case, there is caused a probability that the data in the definite state cannot be latched and unascertained data is transferred to the latch circuit at the next stage, causing a malfunction. Therefore, if delay time TD is increased, the cycle time of clock signal CLK cannot be shortened, making it impossible to achieve high-speed operation.
A configuration aiming to prevent the above-stated racing issue and to decrease the number of components on signal transmission paths is disclosed in, for example, Japanese Patent Laid-Open No. 10-40692(1998).
FIG. 32 is a schematic block diagram showing a structure of a conventional synchronous transfer and processing device. In FIG. 32, cascaded flip-flops FFa to FFc of three stages are shown. Gate circuits AGa to AGc generating control signals are arranged corresponding to flip-flops FFa to FFc, respectively. Each of gate circuits AGa to AGc receives clock signal CLK and a control signal for the flip-flop at the next stage. Specifically, gate circuit AGa receives clock signal CLK and the output signal of gate circuit AGb. Gate circuit AGb receives clock signal CLK and the output signal of gate circuit AGc. Gate circuit AGc receives clock signal CLK and the output signal of a gate circuit provided corresponding to a flip-flop at the next stage which is not shown. The clock signal may be transferred to respective flip-flops FFa to FFc through clock distribution circuitry or may be transferred from a common clock driver.
If a control signal applied to a clock input T from each of corresponding gate circuits AGa to AGc turns H level, each of flip-flops FFa to FFc enters into a latching state and outputs data taken in when the control signal is at L level. That is, if the control signal applied from each of corresponding gate circuits AGa to AGc is at L level, each of flip-flops FFa to FFc takes in data applied to an input D thereof and outputs the taken in data from an output Q.
FIG. 33 shows an example of the configuration of each of flip-flops FFa to FFc shown in FIG. 32. Since flip-flops FFa to FFc have the same configuration, the configuration of a flip-flop FF is representatively shown in FIG. 33. In FIG. 33, flip-flop FF includes an inverter IV 10 which inverts a control signal applied to clock input T, a transfer gate TX10 which is rendered conductive, when the output signal of inverter IV10 is at H level, to pass a signal applied to an input node D, an inverter IV11 which inverts the signal applied through transfer gate TX10, an inverter IV12 which inverts the output signal of inverter IV11, a tri-state inverter buffer IV 13 which is made active, when the signal applied to clock input node T is at the H level, to invert the output signal of inverter IV 11 for transmission to the input of inverter IV11, a transfer gate TX11 which is rendered conductive, when the control signal applied to clock input node T is at H level, to transmit the output signal of inverter IV12, an inverter IV14 which receives the signal applied through transfer gate TX11, an inverter IV 15 which inverts the output signal of inverter IV 14 for transmission to output node Q, and a tri-state inverter buffer IV 16 which is made active, when the output signal of inverter IV 10 is at H level, to invert the output signal of inverter IV14 for transmission to the input of inverter IV14.
Flip-flop FF shown in FIG. 33 consists of latch circuits cascaded in two stages. These latch circuits are alternately set in a latching state and in a transparent state. That is, when the control signal applied to clock input node T is at L level, transfer gate TX10 is rendered conductive, transfer gate TX11 turns nonconductive, and the data applied to input node T is inverted by inverter IV11 and transmitted to inverter IV12. In this state, tri-state inverter buffer IV13 is in an inactive state and in output high-impedance state. Therefore, the output signals of inverters IV11 and IV12 change according to the data applied to input node D. On the other hand, transfer gate TX11 is nonconductive and the data of output node Q does not change.
When the control signal applied to clock input node T attains H level, transfer gate TX10 turns nonconductive, transfer gate TX11 turns conductive and the signal taken in when the control signal is at L level is transmitted to output node Q through inverters IV14 and IV15. In this state, tri-state inverter buffer IV13 is also activated and the previously taken in data is latched by inverter IV11 and tri-state inverter buffer IV13. Therefore, flip-flop FF takes in the data applied to input node D when the control signal applied to clock input node T is at L level, latches the taken in data and outputs the captured data from output node Q when the control signal attains H level.
FIG. 34 is a timing chart representing the operations of the circuit device shown in FIG. 32. In FIG. 34, operations in the case where clock signal CLK applied to flip-flop FFc has the longest delay and clock signal CLK applied to flip-flop FFa has the shortest delay are shown for simplification of description.
When clock signal CLK is at L level, each of gate circuits AGa to AGc outputs a signal at an L level irrespectively of the state of the flip-flop at the next stage. When the control signal applied to clock input node T is at L level, each of flip-flops FFa to FFc takes in data applied to input node D, but the signal at output node Q does not change. When clock signal CLK applied to gate circuit AGc attains H level, the output data of flip-flop FFc changes, transfer gate TX10 connected to input node D of flip-flop FFc turns nonconductive and flip-flop FFc enters a latching state.
When the output signal of gate circuit AGc attains H level, since clock signal CLK is at H level, gate circuit AGb rises the control signal applied to clock input node T of flip-flop FFb to H level. Accordingly, the output data of flip-flop FFb changes and flip-flop FFb enters a latching state.
When the control signal outputted from gate circuit AGb rises to H level, the control signal outputted from gate circuit AGa attains H level, the output signal of flip-flop FFa changes, and flip-flop FFa enters a latching state.
In the circuit device shown in FIG. 32, therefore, after the flip-flop at the next stage enters a latching state, the output data of the flip-flop in the preceding stage changes, thereby preventing erroneous latching of data by the flip-flop at the next stage. That is, as shown in FIG. 32, new data is outputted to the flip-flop at the next stage after this flip-flop turns into a latching state, thereby preventing data from piercing through the flip-flops due to a clock skew as shown in FIG. 35. FIG. 35 shows operations in a case where clock signal CLK applied to flip-flop FFa leads in phase the clock signal CLK applied to flip-flop FFb. As shown in FIG. 35, if a clock skew occurs, when flip-flop FFa turns into a latching state in response to the rise of clock signal CLK, flip-flop FFb is in a signal taking-in state and takes in the output data of flip-flop FFa. Therefore, when clock signal CLK to flip-flop FFb rises, flip-flop FFb turns into a latching state and outputs the output data of flip-flop FFa within the current clock cycle of clock signal CLK. Therefore, data to be transferred after one clock cycle in a correct operation is outputted from flip-flops FFa and FFb in the same cycle, and a malfunction occurs.
It is intended to avoid such data piercing, using gate circuits AGa to AGc shown in FIG. 32.
However, where with the gate circuits shown in FIG. 32, the flip-flop at the next stage enters a latching state and then the corresponding latch circuit enters the latching state in accordance with clock signal CLK to change the output data of the flip-flop, the transmission path of this control signal sequentially propagates the control signal through a series of flip-flops.
It is now considered a data transmission path comprised of flip-flops FF0 to FFn as shown in FIG. 36. Gate circuits AG0 to AGn-1 are provided corresponding to flip-flops FF0 to FFn-1, respectively. Each of gate circuits AG0 to AGn-1 receives corresponding clock signal CLK and a control signal for the flip-flop at the next stage. Flip-flop FFn at the final stage is supplied only with clock signal CLK.
Consider a case where clock signal CLK applied to flip-flop FFn has the longest delay on the data transmission path shown in FIG. 36. In this case, after flip-flop FFn enters a latching state, flip-flop FFn-1 at a preceding stage of flip-flop FFn turns into a latching state and outputs an output signal. Accordingly, in order to set flip-flop FF0 in the first stage in a latching state and to change the output signal of flip-flop FF0, the transmission delays of gate circuits AG0 to AGn-1 are added to the delay time of clock signal CLK. As shown in FIG. 37, therefore, when clock signal CLK applied to flip-flop FFn in the final stage rises to H level after elapse of time Ti since clock signal applied to flip-flop FF0 in the first stage rises to H level, the output signal outputted from gate circuit GA0 attains H level after elapse of signal transmission delay time T2 through gate circuits AG0 to AGn-1. Consequently, the latch circuit in the output stage of flip-flop FF0 in the first stage is required to take in the latch data of the latch circuit in the input stage and transfers the taken-in data to flip-flop FF1 at the next stage within time period T3. However, the setup time of the latch circuit in the output stage of the flip-flop FF0 cannot be sufficiently ensured, with the result that data in an indefinite state may be outputted. If a logical processing circuit is interposed between flip-flops FF0 and FF1, in particular, the processing time of this logical processing circuit cannot be sufficiently secured, with the result that high-speed processing cannot be achieved.
Moreover, the latch time of each of flip-flops cannot be sufficiently secured, leading to a problem that the flip-flops may malfunction.